Skip to product information
1 of 12

PayPal, credit cards. Download editable-PDF and invoice in 1 second!

GB/T 38659.1-2020 English PDF (GBT38659.1-2020)

GB/T 38659.1-2020 English PDF (GBT38659.1-2020)

Regular price $555.00 USD
Regular price Sale price $555.00 USD
Sale Sold out
Shipping calculated at checkout.
Quotation: In 1-minute, 24-hr self-service. Click here GB/T 38659.1-2020 to get it for Purchase Approval, Bank TT...

GB/T 38659.1-2020: Electromagnetic compatibility -- Risk assessment -- Part 1: Electronic and electrical device

This Part of GB/T 38659 provides an overview, objective, mechanism and model of electromagnetic compatibility (EMC) risk assessment for electronic and electrical devices, as well as the influence level of risk elements and risk classification, product risk assessment unit division, EMC risk assessment procedures, EMC risk identification, EMC risk analysis, EMC risk assessment, complete-machine EMC risk level determination and result application, and requirements for risk assessment report.
GB/T 38659.1-2020
GB
NATIONAL STANDARD OF THE
PEOPLE REPUBLIC OF CHINA
ICS 33.100
L 06
Electromagnetic Compatibility - Risk Assessment -
Part 1: Electronic and Electrical Device
ISSUED ON: MARCH 31, 2020
IMPLEMENTED ON: OCTOBER 1, 2020
Issued by: State Administration for Market Regulation;
Standardization Administration of the PEOPLE Republic of
China.
Table of Contents
Foreword ... 3
1 Scope ... 4
2 Normative References ... 4
3 Terms and Definitions ... 5
4 Overview ... 8
5 Objective of EMC Risk Assessment ... 9
6 Mechanism and Model of EMC Risk Assessment ... 9
7 Influence Level of Risk Elements and Risk Classification ... 28
8 Risk Assessment Unit Division ... 33
9 EMC Risk Assessment Procedures ... 34
10 EMC Risk Identification ... 36
11 EMC Risk Analysis ... 39
12 EMC Risk Assessment ... 57
13 Determination and Result Application of Complete-machine EMC Risk Level ... 60
14 Requirements for Risk Assessment Report ... 62
Appendix A (informative) Example of Electromagnetic Compatibility Risk
Assessment ... 63
Appendix B (informative) Example of Attribute Division of Schematic Circuit Diagram ... 70
Bibliography ... 71
Electromagnetic Compatibility - Risk Assessment -
Part 1: Electronic and Electrical Device
1 Scope
This Part of GB/T 38659 provides an overview, objective, mechanism and model of electromagnetic compatibility (EMC) risk assessment for electronic and electrical devices, as well as the influence level of risk elements and risk classification, product risk assessment unit division, EMC risk assessment procedures, EMC risk identification, EMC risk analysis, EMC risk assessment, complete-machine EMC risk level determination and result application, and requirements for risk assessment report. This Part is applicable to electromagnetic compatibility risk assessment of electronic and electrical devices.
This Part combines factors, such as: product?€?s mechanical architecture design, circuit board design and type of application site, to provide guidance for the risk assessment of product?€?s electromagnetic compatibility design.
2 Normative References
The following documents are indispensable to the application of this document. In terms of references with a specified date, only versions with a specified date are applicable to this document. In terms of references without a specified date, the latest version (including all the modifications) is applicable to this document. GB/T 4365 Electrotechnical Terminology - Electromagnetic Compatibility
GB 4943.1-2011 Information Technology Equipment - Safety - Part 1: General Requirements
GB/T 6113.201-2018 Specification for Radio Disturbance and Immunity Measuring Apparatus and Methods - Part 2-1: Methods of Measurement of Disturbances and Immunity - Conducted Disturbance Measurements
GB/Z 18039.1-2019 Electromagnetic Compatibility - Environment - Description and Classification of Electromagnetic Environments
GB/T 18655-2018 Vehicles, Boats and Internal Combustion Engines - Radio Disturbance Characteristics - Limits and Methods of Measurement for the Protection of On-board Receivers
GB/T 23694 Risk Management - Vocabulary
GB/Z 37150 Guide of Risk Assessment of EMC Reliability
3 Terms and Definitions
What is defined in GB/T 4365, GB/T 23694 and GB/Z 37150, and the following terms and definitions are applicable to this document.
3.1 Electromagnetic Compatibility Risk
Electromagnetic compatibility risk refers to the probability of electromagnetic compatibility problems caused by product design. In the test environment, it is the probability of failing the electromagnetic compatibility test.
3.2 Risk Assessment Value
Risk assessment value refers to the value obtained by qualitative and quantitative methods and used to express the magnitude of risks. It is usually between 0 ~ 100. 3.3 Electronic and Electrical Equipment
Electronic and electrical equipment refers to equipment manufactured by electronic technology and that relies on electric current or electromagnetic field to work normally, and equipment that can generate, transmit and measure current and electromagnetic field.
NOTE 1: the design AC voltage of the equipment does not exceed 1,000 V; the design DC voltage does not exceed 1,500 V.
NOTE 2: in accordance with the CISPR product classification, the following equipment belongs to electronic and electrical equipment: engineering medical equipment, multi-media equipment, household appliances, automotive electronic
components, etc.
3.4 Common-mode Current
Common-mode current refers to the vector sum of currents on two or more wires passing through a specified ?€?geometric?€? cross section.
[GB/T 6113.201-2018, Definition 3.1.14]
3.5 Common-mode Interference
Common-mode interference refers to electromagnetic interference (in the same direction) caused by the common-mode voltage of the interference voltage on the signal line and its return line (generally known as signal ground line). electric conductors, such as: wires, coils and casings, and among certain components. NOTE: although its value is small, it is an important cause for common-mode interference. 3.12 High-speed Signal
For digital signal, high-speed signal is determined by the edge speed of the signal. Generally speaking, the signal rise / fall time is less than 4 times the signal transmission delay.
3.13 ?€?Dirty?€? Signal / Electrical Circuit
?€?Dirty?€? signal / electrical circuit refers to signal / electrical circuit that contains signals or parts and components that are easily injected by external interference or generate electromagnetic emissions.
NOTE: for example, signal lines and parts and components that are interconnected with input and output (I/O) cables and are in front of the filter circuit; signal lines of electrostatic discharge (ESD) breakdown discharge that are applied to the surface of the product shell.
3.14 ?€?Clean?€? Signal / Electrical Circuit
?€?Clean?€? signal / electrical circuit refers to signal / electrical circuit that contains signals or parts and components that are neither susceptible to interference nor generate significant electromagnetic interference (EMI) noise.
3.15 Special Signal / Electrical Circuit
Special signal / electrical circuit refers to signal / electrical circuit that contains signals or parts and components that require special processing due to EMC performance. NOTE: it is divided into special noise signal / electrical circuit and special sensitive signal / electrical circuit.
3.16 Noise Signal / Electrical Circuit
Noise signal / electrical circuit refers to signal / electrical circuit that contains signals or parts and components that would easily generate electromagnetic emission disturbance in the field of electromagnetic compatibility.
NOTE: for example, clock signal line, pulse width modulation (PWM) signal line and crystal oscillator, etc.
3.17 Sensitive Signal / Electrical Circuit
Sensitive signal / electrical circuit refers to signal / electrical circuit that contains signals and parts and components that are susceptible to electromagnetic interference in the The 19 main EMC risk elements are provided, which may be used as the key elements in the implementation of product testing and certification to determine whether EMC testing and assessment needs to be re-conducted after a change of product design. 5 Objective of EMC Risk Assessment
The main objective of EMC risk assessment of electronic and electrical equipment includes:
---Recognize EMC risks in product design and their potential impact on the objective;
---Reinforce the understanding of the relevant elements of EMC risks, so as to facilitate the correct selection of risk response strategies;
---Identify the main factors that lead to EMC risks, as well as the weak links of EMC design of electronic and electrical equipment;
---Facilitate the determination of whether EMC risks are acceptable; provide decision makers with quantifiable and relevant information;
---Predict the pass rate of EMC test.
A successful EMC risk assessment of electronic and electrical equipment depends on thorough understanding of design information of the product being assessed and relevant risk elements.
6 Mechanism and Model of EMC Risk Assessment
6.1 Mechanism and Ideal Model of EMC Risk Assessment of Mechanical
Architecture
6.1.1 Mechanism of EMC risk assessment of mechanical architecture
Product?€?s EMC risks include two parts: electromagnetic sensitivity (EMS) and electromagnetic interference (EMI). Specifically speaking, for EMS, its risk assessment mechanism is that when a certain port of the product injects the same magnitude of high-frequency common-mode voltage or the same magnitude of common-mode current, different product design schemes will have different magnitudes of common- mode current flowing through the corresponding circuit structure of the PCB. In the mechanical architecture design, the factors that affect the magnitude of the common- mode current are the EMS risk elements of the product?€?s mechanical architecture. For EMI, its risk assessment mechanism is that when the product is in normal working condition, due to the signal transmission inside the product, the internal useful signal A---the relative position of the cable connector in the circuit board;
B---the overlap joint of the shielding layer of the shielded cable;
C---filtering and protection of the power supply and signal input ports outside the PCB; D---the interconnection between the ?€?0 V?€? ground plane of the PCB board and metal shell (when there is an interconnection);
E---the interconnection of ?€?0 V?€? ground plane among different PCB boards (usually implemented through structural parts);
F---filtering, protection and signal frequency of the internal PCB interconnection signal port of the product;
G---the mode of overlap joint among the various metal parts in the shell (taking the impedance and gap treatment into consideration);
H---the area of loop formed by cables, connectors, PCB (if possible), the interconnection between ?€?0 V?€? ground plane of the PCB board and the metal shell, and the product?€?s metal shell after entering the shell;
I---shell grounding wire.
NOTE: A ~ I are EMC risk elements of product?€?s mechanical architecture. Figure 1 -- EMC Ideal Model of Mechanical Architecture
6.1.3 Requirements for risk elements in EMC ideal model of mechanical
architecture
The risk elements in EMC ideal model of product?€?s mechanical architecture shall satisfy the following relevant requirements of ideal model:
---A: the relative position of the cable connector in the circuit board In the ideal model, the connection position of the cable on the circuit board shall be placed on the same side of a circuit board.
---B: the overlap joint of the shielding layer of the shielded cable
In the ideal model, the cable has a shielding layer, and the connection of the shielding layer needs to satisfy the following requirements:
??? For metal shell products, the cable shielding layer shall be connected to the product?€?s metal shell or metal connector shell at the connector entrance, and form a 360?? overlap;
??? For floating products, the cable shielding layer shall form a 360?? overlap with the ?€?0 V?€? ground plane in the PCB.
---C: filtering and protection of the power supply and signal input port outside the ---F: filtering, protection and signal frequency of the internal PCB interconnection signal port
The requirements for filtering, protection and signal frequency are as follows: ??? F1: in EMS correlation ideal model, the filtering and protection of the PCB interconnection signal ports inside the product
In the ideal model, the signal in all interconnection connectors shall
receive the filtering treatment.
??? F2: in EMI correlation ideal model, the frequency of the PCB
interconnection signals inside the product
In the ideal model, there shall be no high-speed signals, for example,
clock signals or PWM signals in the interconnection signals among the
PCB boards.
---G: the mode of overlap joint among the various metal components of the shell (taking the impedance and gap treatment into consideration)
In the ideal model, the product shell is a perfect shield. In order to implement a perfect shield, then:
??? Implement an intentional overlap among the various metal surfaces of
the shielding body, and;
??? The aspect ratio of each metal body in the shielding body in the
interconnection direction is less than 5, and;
??? The maximum size of the gap or the aperture between the overlap points cannot exceed the minimum size in the following two circumstances:
1) 1/100 of the wavelength of the highest frequency of the circuit;
2) 15 mm.
NOTE 2: intentional overlap refers to the overlap specially designed for EMC objective, such as: screw fastening, welding, riveting, clamping and
connection implemented by filled conductive materials, etc.
---H: the area of loop formed by cables, connectors, PCB (if possible), the interconnection between ?€?0 V?€? ground plane of the PCB board and the metal shell, and the product?€?s metal shell after entering the shell
The loop area is shown in Figure 2. The larger the loop area, the larger the parasitic inductance. The larger inductance will hinder the discharge of interference current.
3---?€?clean?€? signal / electrical circuit area;
4---special signal / electrical circuit area (including internal noise signal / electrical circuit area, sensitive signal / electrical circuit area);
5---ground plane.
Figure 7 -- Schematic Diagram of Construction of EMC Ideal Model of PCB In order to implement the ideal model shown in Figure 7, PCB needs to be performed from two parts: schematic circuit diagram and PCB layout. The implementation of the ideal model of the schematic circuit diagram is established on the attribute division of the schematic circuit diagram. In accordance with the requirements of Figure 7, if the schematic circuit diagram corresponding to the PCB can be divided into categories 1, 2, 3, 4 and 5 (in which, ground plane is one of the categories), and the parameters are correct, then, it is deemed that the EMC design of schematic circuit diagram complies with the ideal model. Among then, the divided Category 2 of signals and circuits are the processing measures between each category of signal and circuit on the schematic circuit diagram, which respectively are:
a) The filtering on the ?€?dirty?€? signal line is generally between the ?€?dirty?€? signal and the clean signal.
b) On special signal lines, the filtering on the sensitive signals and the filtering on the special noise signals are included. The filtering on the sensitive signals is generally between the sensitive signals / electrical circuit and clean signals / electrical circuit. The filtering on the special noise signals is generally between the special noise signals / electrical circuit and clean signals / electrical circuit.
In addition, the processing on clean lines and the capacitance jump between different isolated grounds are also part of the implementation of the ideal model of the schematic circuit diagram.
The implementation of the EMC ideal model of PCB layout is based on the attribute division of the schematic circuit diagram. Each signal layer is implemented as shown in Figure 7 and through the following measures:
a) Minimize the impedance of the complete PCB ground plane;
b) No crosstalk occurs between signal lines of different attributes;
c) The edge of the signal layer and power layer is grounded, so as to prevent edge effects (reduce the parasitic capacitance between the signal line and the power line, and the reference ground).
See the specific content in 6.2.2.2 ~ 6.2.2.3.
---K: special sensitive signal / electrical circuit area and noise signal / electrical circuit area
??? K1 special sensitive signal / electrical circuit area
In the ideal model, this type of special sensitive signal line / electrical circuit needs the filtering treatment. The filter circuit is at least on the input ports of the following signal lines:
a) Signal line with high input impedance;
b) Low-level analog signal line;
c) All signals in the interconnection line between PCB boards.
??? K2 special sensitive signal / electrical circuit area
In the ideal model, this type of special noise signal / electrical circuit requires special treatment. The measures of the special treatment shall satisfy:
a) De-couple any power pins of digital chip;
b) Control the signal rising time of special noise signal lines, such as: clock line, PWM and UVW to the minimum within the range allowed
by the function; in addition, ensure the signal integrity and prevent
overshoot;
c) When this type of area circuit is simultaneously the circuit of ?€?dirty?€? signal / electrical circuit area, then, the cable connected to the signal needs to be shielded.
Specially speaking, de-coupling is usually the circuit between the power supply pin of the internal chip of digital circuit in the PCB and the power supply network of the PCB. For the circuit between the power supply of the PWM power circuit in the PCB and the ground (for example, the energy storage capacitor in the switching power supply), de-coupling is an effective way of reducing the chip power supply noise, which shall satisfy:
a) There is at least one de-coupling capacitor between each power pin
of the chip and the ground, and;
b) There is at least one de-coupling capacitor between the power supply of the PWM power circuit and the ground, and;
c) The magnitude of the de-coupling capacitor is usually determined by
the operating frequency of the device. When the frequency is greater
than 2 MHz, adopt 0.1 ??F de-coupling capacitor. In a circuit with a
reducing the ground impedance. When considering EMS, the ideal model
of PCB layout design is as follows:
a) There shall be a ground plane layer; and
b) The following areas also require a complete ground plane:
1) On the discharge path of common-mode current;
2) Between the ground pins of two devices, through which, the
common-mode current flows (except the ground pins of the
module power supply);
3) Between the filter capacitor and bypass capacitor on the port,
and the interconnection point of the shell.
A complete plane means a piece of PCB copper foil without any via
holes, slots or cracks, and with an aspect ratio less than 3.
??? R2: EMI correlation ground plane processing
The complete ground plane design of PCB is an effective measure of
reducing the ground impedance. In the ideal model:
a) All signal layers are adjacent to the complete plane (ground plane or power plane); and
b) The power plane is adjacent to its corresponding ground; and
c) The layer thickness is set to the minimum under the premise of
satisfying impedance control; and
d) The following areas also require a thoroughly connected ground
plane:
1) Below the special noise signal / electrical circuit, and use copper
foil connected to the ground to enclose some lines;
2) The interconnection lines among the filter capacitor, chip de-
coupling capacitor, bypass capacitor on the port, and the ground.
NOTE: a complete plane means a piece of PCB copper foil without any via holes, slots or cracks, and with an aspect ratio...

View full details